View HMP9701A_340656.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Semiconductor
November 1998
CT UCT ODU ROD E PR ITUTE P 2-7747 T T OLE 44 OBS LE SUBS s 1-800- m IB ion arris.co at SS pplic A PO @h FOR Central A centapp call r email: o
HMP9701A
AC'97 Audio Codec
Features
* Compliant with the Audio Codec `97 Standard
Description
The HMP9701A is the next generation PC based audio codec solution. The HMP9701A is compliant to the new AC'97 stan* High Fidelity 16-Bit Converters dard and, as such, interfaces to any AC'97 compliant digital [ /Title (HMP9701A) - DAC SNR 87dB controller. The HMP9701A offers the designer a solution to sat/Subject SNR 85dBAudio Codec) - ADC (AC'97 isfy the demand for flexibility and improved High Fidelity sound /Author () in a PC environment. As part of the AC'97 PC audio standard * Additional A/D for Microphone Pass-Through architecture, the HMP9701A helps pave the way for PC'97 /Keywords (Harris Semiconductor, Audio Codecs, PC * AC Link Serial Interface Compatible with AC'97 Digital Audio, PC'98, PC98, PC 98, PC'99, PC 99, PC99, compliant desktop, portable and entertainment PCs with a cost Controllers effective high-quality audio solution. THD, PCI Audio, AC97, AC'97, AC 97, AC'98, AC 98, * Fixed 48kHz Sampling Rate As the analog front end of the AC'97 chipset, the HMP9701A * 6 Channel Input Mixer
AC98, SNR, AC Link, PC'97, PC 97, PC97, GAM accepts line level audio inputs from seven different sources and PCI Sound, Total Harmonic Distortion, Signal to Noise converts the analog audio to 16-bit digital streams of either ste* Programmable Powerdown Modes Ratio, Record Gain reo or mono data. The 48 kss data is transmitted to the controller via the AC'97 standard five wire interface. The controller ) * 48 Lead TQFP Package sends digital audio data to the HMP9701A to be converted to /Creator () * Single +5V Supply analog stereo or monaural line output using two DACs. /DOCINFO pdfmark We include an additional ADC to be used for Acoustic Echo Applications Canceling needed for video conferencing applications. This [ /PageMode /UseOutlines ADC has a dedicated microphone input. It has the same high * Multimedia PC Applications quality performance as the stereo ADCs. The small 48 lead /DOCVIEWPCs pdfmark - Desk Top
- Notebook PCs - PCI Sound Cards - Motherboards * Video Conferencing * Speaker Phones TQFP (Thin 1.5mm and 7mm x 7mm footprint Quad Flat Package) makes it easy to locate the analog codec close to the analog sources. Thus, reducing noise and lowering the cost of implementation.
Ordering Information
Page
PART NUMBER HMP9701ACN HMP9701EVAL2 TEMP. RANGE (oC) 0 to 70 PACKAGE 48 Ld TQFP PKG. NO. Q48.7x7A
Table of Contents
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Serial Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . 8 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 AC and DC Electrical Specifications . . . . . . . . . . . . . . . . . 13 ADC/DAC Filter Response Curves . . . . . . . . . . . . . . . . . . 17 AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Schematic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PCI Bus Evaluation Board (Includes codec)
TQFP is also known as PQFP and MQFP.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
(c) Harris Corporation 1998
File Number
4473.1
1
HMP9701A Functional Block Diagram
HMP9701A AC'97 AUDIO CODEC
MIC1 MIC2 LINE_IN CD VIDEO AUX PHONE
MIC SEL
GAIN 0dB/20dB A/D RECORD SELECT RECORD GAIN A/D A/D
MONO SEL
MONO_OUT
MONO VOL G A M MASTER VOL GAM
G A M G A M G A M G A M G A M
AC'97 CONTROL/CONFIGURATION (64 REGISTERS)
AC LINK INTERFACE
SYNC BIT_CLK SDATA_OUT SDATA_IN RESET

GAM D/A D/A
LINE_OUT
PC_BEEP
STEREO SIGNAL PATH MONO SIGNAL PATH
Functional Description
The HMP9701A is a full-duplex stereo audio codec compliant to the AC'97 Codec specification. This component is designed for use in multimedia and business personal computers. The codec includes full duplex stereo converters, a mic pass through ADC, complete on-chip anti-alias filtering, and a 5 channel analog mixer with programmable gain and attenuation. Analog Inputs The HMP9701A has 4 stereo inputs (LINE_IN, CD, VIDEO, and AUX), two microphone level inputs (MIC1 and MIC2), and one mono line level input (PHONE). A multiplexer is provided to independently select the right and left record sources from the analog inputs listed above. In addition, the output stereo mix (LINE_OUT) or its mono equivalent may also be selected as a record source. A gain block is available to amplify the MIC inputs by 20dB to compensate for the difference between line levels and typical condenser microphone levels. Besides being fed to the Record Select Mux, all analog inputs can be mixed (see Analog Mixer) with the stereo output from the Playback DACs. Note: all analog inputs except PHONE and PC_BEEP can be output on MONO_OUT. There is a dedicated analog input, PC_BEEP, for the standard "Beep" signal provided on most PC/Compatible computers for power on self test and boot audio status indication. This input is mixed into each channel of the stereo line outputs. Record ADCs The HMP9701A provides 3 ADCs to record one dedicated microphone input and 2 user selectable analog inputs. The user selectable analog inputs are routed to the stereo ADCs via an programmable Input Multiplexer. The multiplexer is programmed to select the 2 record channels via the Record Select register (1Ah). Each of the record channels pass through a programmable gain block before each ADC. The record gain for each channel is set individually and ranges from 0dB to 22.5dB in 1.5dB increments (see Record Gain Registers 1Ch and 1Eh). The gain block can also be used to mute each channel. Note: an additional gain block provides 20dB of gain on the MIC channel if activated (see MIC Volume register 0Eh). The HMP9701A uses oversampling ADCs which only require a single pole passive filter for anti-alias filtering. The filter for the left, right and MIC channels is realized by placing a 1nF capacitor between the AFILT1, AFILT2, and AFILT3 pins and analog ground respectively. Playback DACs The HMP9701A uses oversampling single bit DACs to convert the stereo playback sample to an analog line level output. The output of the DACs pass through internal reconstruction filters that do not require any external components.
2
HMP9701A
Analog Mixer The Analog Mixer generates two outputs, one stereo and one mono. The stereo output is used to drive LINE_OUT and is composed of a stereo mix of all analog input sources and the audio output from the DACs. The mono output drives MONO_OUT, and it is user selectable as either MIC only or a mono mix of all the analog and PCM sources except the PHONE and PC_BEEP inputs. The inputs to the analog mixer pass through gain/attenuate/mute (GAM) blocks. Each gain block provides volume control from -34.5dB to +12dB in 1.5dB increments (see Input Volume Registers 0Ch - 18h). Additionally, the GAM blocks can be used to mute individual mixer inputs. An additional gain of 20dB is provided for the selected MIC input. Note: for best SNR performance, the GAM block for the DAC output should be used to control PCM analog volume rather than digitally attenuating the DAC PCM input to take advantage of full resolution conversions. Clocking The HMP9701A derives it's internal clock from an externally attached 24.576MHz crystal. The crystal and 2 capacitors are attached to the XTL_IN and XTL_OUT pins, and it should be fundamental-mode/parallel resonant with a load capacitor as specified by the crystal manufacturer (typically 12-30pF). For an example circuit, refer to the Typical Application Schematic. An external CMOS clock may be connected to XTL_IN instead of a crystal. If this external clocking option is used, XTL_OUT should be left floating. Please Note: No capacitors are used on the crystal pins in this mode. The HMP9701A divides the clock source by 2 to derive the BIT_CLK provided to the companion digital controller. The digital controller should divide the provided BIT_CLK by 256 to generate the 48kHz SYNC signal used to define the audio frame transmitted over the serial digital interface (See Serial Digital Interface Section)
FIGURE 1. HMP9701A CONNECTION TO AC'97 CONTROLLER
Serial Digital Interface
Audio Data Format The HMP9701A supports 16-bit 2's complement linear PCM data for record and playback. The 16-bit 2's complement format (also called 16-bit signed format) is the standard method of representing 16-bit digital audio. This format gives 96dB theoretical dynamic range and is the standard for compact disk audio players. This format uses the value -32768 (8000h) to represent minimum analog amplitude while 32767 (7FFFh) represents maximum analog amplitude.
SYNC BIT_CLK AC'97 DIGITAL CONTROLLER SDATA_OUT SDATA_IN HMP9701A AC'97 AUDIO CODEC
RESET
Digital Serial Interface (AC Link) The HMP9701A is linked to an AC'97 digital controller via a 5 pin digital serial interface as shown in Figure 1. This interface, the AC-link, supports bidirectional, fixed rate, serial data streams. The data transfers are based on a time division multiplexed (TDM) protocol that provides for multiple input and output audio streams together with control and status data. The AC-link protocol is based on incoming and outgoing audio frames which are each divided into 12 data slots as shown in Figure 2. The HMP9701A allocates data slots for 2 PCM playback channels, 2 PCM record channels, codec control, codec status, and a PCM microphone record channel. The remaining unused time slots are reserved.
SLOT NO. SYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
OUTGOING AUDIO STREAMS
TAG
CMD ADDR
CMD DATA
PCM LEFT
PCM RIGHT
RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD
INCOMING AUDIO STREAMS
TAG
STATUS STATUS ADDR DATA
PCM LEFT
PCM RIGHT
RSRVD
MIC
RSRVD RSRVD RSRVD RSRVD RSRVD RSRVD
TAG PHASE
DATA PHASE
FIGURE 2. AC LINK BIDIRECTIONAL DATA FRAME
3
HMP9701A
20.8s (48kHz) TAG PHASE DATA PHASE
SYNC
12.288MHz 81.4ns
BIT_CLK SLOT SLOT 1 2 SLOT 12
SDATA_OUT VALID FRAME
"0"
"0"
"0"
BIT 19
BIT 0 BIT 19
BIT 0
BIT 19
BIT 0
TIME SLOT "VALID" BITS ("1" = TIME SLOT CONTAINS VALID DATA)
SLOT 1
SLOT 2
SLOT 12
"1" = FRAME CONTAINS VALID DATA
FIGURE 3. AC LINK AUDIO OUTPUT FRAME
The HMP9701A generates a serial bit clock (BIT_CLK) at 12.288MHz for synchronous data transfers on the AC Link. Data is output on SDATA_IN by the rising edge of BIT_CLK, and serial data is sampled on SDATA_OUT by the falling edge of BIT_CLK. An audio frame transfer is initiated by the assertion of SYNC for the 16 BIT_CLK's comprising the Tag Phase of the audio frame. The SYNC signal must be asserted at a fixed 48kHz rate, and it can be derived by dividing down the BIT_CLK. The tag phase is a 16-bit data slot (Slot 0) wherein each bit is a data valid flag for an associated time slot within the current audio frame. A "1" in a given bit position of Slot 0 indicates that the corresponding time slot within the audio frame contains valid data. If the HMP9701A "tags" a slot invalid, it will set the data bits comprising that slot to zero. AC Link Output Frame (SDATA_OUT) The audio output frame contains data targeted for the HMP9701A's DAC inputs, and control registers. This data is transmitted in slots 1 through 4 of the audio frame as shown in Figure 2. The tag slot, Slot 0, is a special reserved time slot containing 16 bits that tell the AC-link interface circuitry the validity of the following data slots. The HMP9701A is synchronized to the beginning of a new audio output frame when SYNC makes a low to high transition and is sampled low by the falling edge of BIT_CLK as shown in Figure 3. On the next rising of BIT_CLK, the AC'97 controller drives SDATA_OUT with the first bit of slot 0 (Valid Frame bit) which is then sampled by the HMP9701A on the subsequent falling edge of BCLK. The controller drives the remaining audio frame bits out on SDATA_OUT with each rising edge of BCLK, and the HMP9701A samples these bits on the subsequent falling edge. The first bit of the output audio frame (Slot 0, bit 15) flags the validity of the entire audio frame. If the "Valid Frame" bit is a 1, this indicates that the current audio frame contains at least one time slot of valid data. The HMP9701A monitors the next 4-bit positions to determine whether the data
in the control and PCM output data slots is valid. The remaining 8 bits in Slot 0 are ignored as they are associated with reserved data slots.
HMP9701A SAMPLES SYNC ASSERTION SYNC HMP9701A SAMPLES FIRST BIT OF AUDIO OUTPUT
BIT_CLK
SDATA_OUT
SLOT 1 VALID FRAME
SLOT 2
PREVIOUS AUDIO FRAME
FIGURE 4. START OF AUDIO OUTPUT FRAME
The 20-bit data word in each time slot must be transmitted MSB first. If the data word targeted for a time slot is less than 20 bits, the data word must be MSB justified in the most significant bits of the time slot with the unused bits set to zero. For example, an 8-bit audio sample would be transmitted in bits 19-12 of the time slot with the trailing 12 bits set to zero. The MSB of the audio sample would map to bit 19 of the time slot. Note: for the playback of mono audio streams, the digital controller must send the same sample to each PCM output channel. Audio Output Slot 1: Control Address The bits in Slot 1 are used to access the 16-bit control/status registers within the HMP9701A. The address space allocated in slot 1 allows up to 64 sixteen bit registers, however, only the even registers are valid (see Control/Status register section for a complete register map). The control registers are read/writable to provide more robust testability. A read or write command is initiated by setting the Read/Write bit (Bit 19) in Slot 1. A complete bit map for Slot 1 is given in the Table 1. Note: control data will only be loaded into the target registers if Slot 2 (Control Data) is flagged as being valid.
4
HMP9701A
TABLE 1. BIT MAP FOR SLOT 1: CONTROL ADDRESS BITS 19 DESCRIPTION Read/Write COMMENT 1 = Read, 0 = Write Identifies the Target Control Register Set to "0"
samples are returned in slots 3, 4 and 6 as shown in Figure 2. As before, the tag slot, Slot 0, is a special reserved time slot containing 16 bits that tell the AC-link interface circuitry the validity of the following data slots. The HMP9701A starts a new audio input frame when SYNC makes a low to high transition and is sampled low by the falling edge of BIT_CLK as shown in Figures 5 and 6. On the next rising edge of BIT_CLK, the HMP9701A drives SDATA_IN with the first bit of slot 0 (Codec Ready bit). The HMP9701A drives the remaining audio frame bits out on SDATA_IN with each rising edge of BIT_CLK. Note: SYNC must be synchronous to BIT_CLK.
HMP9701A SAMPLES SYNC ASSERTION SYNC HMP9701A OUTPUTS FIRST BIT OF AUDIO INPUT FRAME
18:12 Control Register Index 11:0 Reserved
Audio Output Slot 2: Control Data This Slot is used to deliver the 16-bit control data if the current control register access is a write operation (Bit 19 of Slot 1 is set to "0"). The bit map for Slot 2 is given in Table 2.
TABLE 2. BIT MAP FOR SLOT 2: CONTROL DATA BITS 19:4 3:0 DESCRIPTION Control Register Write Data Reserved COMMENT Set to "0" if Read operation Set to "0"
BIT_CLK
Audio Output Slot 3: PCM Playback Left Channel This time slot contains the audio sample that will be input to the left channel DAC. The HMP9701A DAC resolution is 17 bits. All audio samples of 17 or less bits should be MSB justified within the 20-bit frame, and the trailing bits should be set to "0". Audio samples greater than 17 bits will be rounded to 17 bits.
TABLE 3. BIT MAP FOR SLOT 3: PCM PLAYBACK LEFT CHANNEL BITS 19:0 DESCRIPTION PCM Audio Sample for Left Channel COMMENT Set unused bit positions to "0"
SDATA_IN CODEC READY SLOT 1 SLOT 2
PREVIOUS AUDIO FRAME
FIGURE 5. START OF AUDIO INPUT FRAME
Audio Output Slot 4: PCM Playback Right Channel This time slot contains the audio sample that will be input to the right channel DAC. The DAC's resolution is 17 bits. All audio samples of 17 or less bits should be MSB justified within the 20-bit frame, and the trailing bits should be set to "0". Audio samples greater than 17 bits will be rounded to 17 bits.
TABLE 4. BIT MAP FOR SLOT 4: PCM PLAYBACK RIGHT CHANNEL BITS 19:0 DESCRIPTION PCM Audio Sample for Right Channel COMMENT Set unused bit positions to "0"
The first bit of an input audio frame (Slot 0, bit 15) indicates whether the HMP970's AC Link is functional. If the "Codec Ready" bit is a 0, the HMP9701A is not ready for normal operation. If the "Codec Ready" bit is "1", the HMP9701A is ready to perform control and status register transfers. At this point, it is the responsibility of the digital controller to examine the Powerdown Control/Status register (see Control Register Section) to determine the operational state of the codec subsections. The 12 bits following the "Codec Ready" Bit in Slot 0 identify which of the 12 time slots contain valid data. The HMP9701A outputs each time slots data word MSB first on SDATA_IN. All non-valid bit positions (for active or inactive time slots) are stuffed with 0's by the HMP9701A. Input Audio Slot 1: Status Address This slot echoes the index of the control register whose contents are returned in slot 2. The data in this register is the result of a control register read operation initiated by an Output Audio Frame transfer.
TABLE 5. BIT MAP FOR SLOT 1: STATUS ADDRESS BITS 19 18:12 DESCRIPTION Reserved Control Register Index Reserved COMMENT Stuffed with 0 Echo of Control Register Index for which data is being returned Stuffed with 0's
Audio Output Slots 5-12: Reserved Audio output slots 5-12 are reserved for future use and should be set to "0" for proper operation. AC Link Input Frame (SDATA_IN) The audio input frame contains captured audio samples and codec status for output onto the AC-Link. The codec status is transmitted in slots 1 and 2, and the 16-bit captured audio
11:0
5
HMP9701A
Input Audio Slot 2: Status Data This slot delivers control register read data.
TABLE 6. BIT MAP FOR SLOT 1: STATUS DATA BITS 19:4 DESCRIPTION Control Register Read Data Reserved COMMENT Stuffed with 0's if slot tagged invalid TABLE 9. BIT MAP FOR SLOT 6: MICROPHONE RECORD DATA Stuffed with 0's BITS 19:4 DESCRIPTION PCM Record Sample Microphone Channel Reserved COMMENT 16-Bit Audio Sample From Dedicated Microphone ADC Stuffed with 0's
Input Audio Slot 6: Microphone Record Channel This slot contains an audio sample captured by the dedicated microphone ADC. The resolution of the ADC is 16 bits and is MSB justified in the 20-bit slot. This input allows higher performance echo cancellation algorithms in speaker phone applications.
3:0
Input Audio Slot 3: PCM Record Left Channel This slot contains an audio sample captured by the left channel ADC. The resolution of the ADC is 16 bits and is MSB justified in the 20-bit slot.
TABLE 7. BIT MAP FOR SLOT 3: LEFT CHANNEL RECORD DATA BITS 19:4 DESCRIPTION PCM Record Sample Left Channel Reserved COMMENT 16-Bit audio sample from Left Record ADC Stuffed with 0's
3:0
Slots 5, 7-12: Reserved Audio input slots 5, and 7-12 are reserved, and they are set to "0".
Low Power Modes
The HMP9701A may be put in a programmable powerdown state to reduce power when no activity is required. The state of powerdown is controlled by the Powerdown Register (26h). This register provides 6 commands to powerdown various sections of the HMP9701A. A summary of the power down commands is given in Table 10 with a more complete description given in the Control Register Section. Note, the HMP9701A is a fully static design which will preserve the contents of the internal control registers if the internal clock is stopped.
TABLE 10. SUMMARY OF POWERDOWN REGISTER (26H) BIT PR0 FUNCTION Input Mux and ADC Powerdown DAC Powerdown Analog Mixer Powerdown (VREF On) Analog Mixer Powerdown (VREF Off) Digital Interface (AC-Link) Powerdown (External CLK Off) Internal CLK Disable
3:0
Input Audio Slot 4: PCM Record Right Channel This slot contains an audio sample captured by the right channel ADC. The resolution of the ADC is 16 bits and is MSB justified in the 20-bit slot.
TABLE 8. BIT MAP FOR SLOT 4: RIGHT CHANNEL RECORD DATA BITS 19:4 DESCRIPTION PCM Record Sample Right Channel Reserved COMMENT 16-Bit audio sample from Right Record ADC Stuffed with 0's
PR1 PR2
3:0
PR3 PR4 PR5
20.8s (48kHz) TAG PHASE DATA PHASE
SYNC
12.288MHz 81.4ns
BIT_CLK SLOT SLOT 1 2 SLOT 12
SDATA_IN CODEC READY
"0"
"0"
"0"
BIT 19
BIT 0 BIT 19
BIT 0
BIT 19
BIT 0
TIME SLOT "VALID" BITS ("1" = TIME SLOT CONTAINS VALID DATA)
SLOT 1
SLOT 2
SLOT 12
"1" = AC LINK INTERFACE IS FUNCTIONAL
FIGURE 6. AC LINK AUDIO INPUT FRAME
6
HMP9701A
AC Link Powerdown The AC-link interface can be placed in a low power mode by setting PR4 = 1 in the Powerdown Register (see above). In this mode, both BIT_CLK and SDATA_IN are forced to a logic "low" voltage level.
SYNC
Suggested Powerdown Sequences
PR0=1
PR1=1
PR2=1
PR4=1
NORMAL
ADCs OFF PR0 PR1=0 AND DAC=1
DACs OFF PR1
ANALOG OFF PR2 OR PR3 PR2=0 AND ANL=1
AC LINK OFF PR4
POWER DOWN
BCLK SDATA_OUT SLOT 12 TAG WRITE TO 26H DATA PR4 = 1
PR0=0 AND ADC=1
WARM RESET
SDATA_IN
SLOT 12
TAG
CODEC READY =1
COLD RESET DEFAULT
PREVIOUS FRAME
NOTE: BCLK not to scale. FIGURE 7. AC-LINK POWERDOWN TIMING
FIGURE 8. EXAMPLE OF SEQUENTIAL POWERDOWN
As shown in Figure 7 BIT_CLK and SDATA_IN are driven low immediately following the decode of the write to the Powerdown Control/Status Register (26h) with PR4 = 1. Once HMP9701A has been instructed to powerdown the AC Link, a special "wake up" sequence is required to return the ACLink to active mode. Note: any valid slots of audio output samples in the frame containing the AC Link powerdown command will be dropped. Waking up the AC-Link There are 2 methods for bringing the HMP9701A's AC-link out of powerdown mode. The first is a "warm reset" that preserves reactivates the AC Link while preserving the contents of the HMP9701A control registers. The second is a "Cold Reset" that reactivates the digital interface while resetting the control registers to their default values. Once the AC Link has been powered up, its operational readiness will be indicated via the Codec Ready bit in the audio input frame (slot 0, bit 15). Warm AC Link Reset A warm reset will reactivate the HMP9701A's AC-link without altering the current control register values. A warm reset is generated by driving SYNC high for a minimum of 1s in the absence of BIT_CLK. Within normal audio frames SYNC is a synchronous BIT_CLK. However, in the absence of BIT_CLK, SYNC functions as an asynchronous input that is used to generate a warm reset. The activation of BIT_CLK will not occur until after the falling edge (high to low transition) of the "wake up" SYNC. Note: the HMP9701A will not respond to a "warm reset" via the SYNC input for 4 audio frame times following the frame that triggered the powerdown. Cold AC Link Reset A cold reset is achieved by asserting RESET for a minimum of 1s. By driving RESET low, BIT_CLK will be activated, the AC-Link will return to normal operation, and all HMP9701A control registers will be initialized to their default values. RESET is an asynchronous HMP9701A input. Note: the HMP9701A will remain in the reset state as long as RESET is asserted "low".
Figure 8 illustrates the complete powerdown of the HMP9701A. Starting from normal operation, sequential writes to the Powerdown Register are performed to powerdown one codec section at a time. After powering down the converters and the analog front end, a final write to PR4 is executed to shut down the HMP9701A's digital interface (AC-link). The part will remain in sleep mode with all its registers holding their static values. A warm reset can be used to wake up the AC link which can then be used to sequentially power up each codec section. Each section should be powered up sequentially, and the Powerdown Control/Status register (26h) should be read to verify that a powered up section is stable/ready before preceding to power up the next section as shown in Figures 8 and 9. Note: after a complete powerdown, care must be taken to make sure the Analog Mixer (PR2, PR3) is powered up and stable before preceding to power up the ADCs and DACs.
PR0=1
PR1=1
PR4=1
NORMAL
ADCs OFF PR0 PR1=0 AND DAC=1
DACs OFF PR1
AC LINK OFF PR4 WARM RESET
POWER DOWN
PR0=0 AND ADC=1
FIGURE 9. HMP9701A POWERDOWN/UP WITH ANALOG ALIVE
The Figure 9 illustrates an HMP9701A powerdown sequence that will keep all the mixers operational with the static volume settings contained in their associated registers. This powerdown scenario could be used to place the HMP9701A in low power mode while preserving the capability to play a CD (or external LINE_IN source) through the HMP9701A to the speakers.
7
HMP9701A Testability
The HMP9701A provides a test mode to support the in circuit test capabilities provided by automatic test equipment (ATE). In this mode, the HMP9701A drives its digital AC-Link outputs (BIT_CLK and SDATA_IN) to a high impedance state. This allows for in circuit testing of the digital controller component of the sound subsystem. The HMP9701A enters ATE test mode when SDATA_OUT is sampled high by the trailing edge of RESET (see AC Timing Diagrams). The HMP9701A will remain in test mode until a "cold" reset returns the part to normal operation. PC Beep Register (Index 0Ah) This register controls the level of the PC Beep input. The PC Beep is attenuated as specified by the contents of this register and mixed equally into both the right and left output channels. The PC_BEEP input is attenuated in 3dB steps from 0dB to 45dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel is set at - dB.
TABLE 12. PC_BEEP ATTENUATION SETTINGS MUTE 0 0 PV3:0 0000 1111 xxxx FUNCTION 0dB Attenuation 45dB Attenuation -dB Attenuation
Control/Status Registers
The HMP9701A contains a bank of 16-bit control/status registers to control and monitor part operation. The control registers are accessed via the even addresses within the 6-bit address space provided in Slot 1 of the Audio Output Frame. The control/status register address map is given in Table 20. Reset Register (Index 00h) Writing any value to this register performs a register reset that causes all registers to revert to their default values. Reading this register returns the AC'97 ID code that specifies the optional AC'97 features supported by the HMP9701A. This register will read back 0001h to indicate that the HMP9701A provides the optional ADC for a dedicated MIC channel. Master Volume Control Registers (Index 02h, 06h) These registers manage the output audio volumes. Register 02h sets the master stereo volume (LINE_OUT_L, LINE_OUT_R) and Register 06h controls the mono volume (MONO_OUT). Each volume step corresponds to 1.5dB. The MSB of both registers is the mute bit. When this bit is set to 1 the level for that channel is set at -dB.
TABLE 11. MASTER VOLUME SETTINGS MUTE 0 0 0 1 MX5...MX0 00 0000 01 1111 1x xxxx xx xxxx FUNCTION 0dB Attenuation 46.5dB Attenuation 46.5dB Attenuation -dB Attenuation
1
Default Value: 8000h (0dB Gain w/ Mute on)
Input Volume Control (Index 0Ch- 18h) These registers control the input gain/attenuate/mute (GAM) blocks through which each of the analog mixer's inputs pass. Each GAM block has a 5-bit control that supports setting the gain in increments of 1.5dB. A total gain range from +12dB to -34.5dB is supported. The MSB of each register is a Mute bit that will set the gain to -dB when programmed to 1. Note: register 0Eh (Mic Volume Register) has an extra bit that is for a 20dB boost. When bit 6 is set to 1 the 20dB boost is on.
TABLE 13. ANALOG MIXER INPUT GAIN SETTINGS MUTE 0 0 0 1 PV3:0 00000 01000 11111 xxxx FUNCTION +12dB Gain 0dB Gain -34.5dB Gain -dB Gain
Default: All GAM blocks set to Mute with 0dB Gain (see Table 20)
Record Select (Index 1Ah) This register is used to select the record source for the left and right record ADC's. The selections are summarized below in Table 14 and 15.
TABLE 14. RECORD SELECT RIGHT CHANNEL SR2:0 0 1 2 RIGHT RECORD SOURCE MIC CD_R VIDEO_R AUX_R LINE_IN_R Stereo Mix Right Mono Mix PHONE
Default Value: 8000h (0dB Gain with Mute On)
The HMP9701A supports 5 bits of gain control for the stereo line out and mono out. The right and left stereo channels are controlled via MR4:0 and ML4:0 respectively. The mono output is controlled by MM4:0. Writing a "1" to MR5, ML5, or MM5 will force the volume level to max attenuation, Mx4:0 = 11111 (46.5dB attenuation). Note: if these registers are written with Mx5:0 = 1xxxx, they will read back Mx5:0 = 01111.
3 4 5 6 7 Default: 000 (MIC in)
8
HMP9701A
TABLE 15. RECORD SELECT LEFT CHANNEL SL2:0 0 1 2 3 4 5 6 7 Default: 000 (MIC in) RIGHT RECORD SOURCE MIC CD_L VIDEO_L AUX_L LINE_IN_L Stereo Mix Right Mono Mix PHONE PR5 PR3 PR4 BIT PR0 PR1 PR2 TABLE 18. POWERDOWN CONTROL FUNCTION Input Mux and ADC's (1 = PWR Down, 0 = PWR Up) DACs (1 = PWR Down, 0 = PWR Up) Analog Mixer Powerdown with VREF Left On (1 = PWR Down, 0 = PWR Up) Analog Mixer Powerdown with VREF Turned Off (1 = PWR Down, 0 = PWR Up) Digital Interface (AC Link) powerdown (BCLK off) (1 = PWR Down, 0 = PWR Up) Internal Clock Disable (1 = CLK Off, 0 = CLK On)
Default: na
Record Gain Registers (Index 1Ch and 1Eh) These registers control the record gain for both the MIC input and the selected stereo inputs (see Record Select Register). The gain is programmed in steps of 1.5dB and ranges from 0dB to +22.5dB. The MSB of the register is the mute bit. When this bit is set to 1 the level for that channel(s) is set at -dB.
TABLE 16. RECORD GAIN SETTINGS MUTE 0 0 1 PV3:0 0 1111 0 0000 x xxxx FUNCTION +22.5dB Gain 0dB Gain -dB Gain
The lower byte of this register is used to monitor the status of individual sections with in the HMP9701A. The status bits, as summarized in Table 19, indicate whether a subsection is in it's normal operational state (Ready). Note: the status bits are read only, and writes to this register will have no effect on the state of these bits.
TABLE 19. POWERDOWN STATUS BIT REF ANL DAC ADC FUNCTION VREFs at Nominal Level (1 = VREF Ready, 0 = VREF Down) Analog Mixer Powerdown (1 = Mixer Up, 0 = Mixer Down) DAC Ready for Audio Samples (1 = Ready, 0 = Not Ready) ADC Section Ready to Record (1 = Ready, 0 = Not Ready)
Default: 8000h (0dB Gain with Mute on)
General Purpose Register (Index 20h) This register is used to control several miscellaneous functions within the HMP9701A. These include the selection of Mic input source, the selection of MONO_OUT source, and activation of ADC/DAC loopback mode. When loopback mode is enabled, the ADC output is looped back to the DAC input bypassing the AC-link, thus allowing for full system performance measurements.
TABLE 17. GENERAL PURPOSE CONTROL BIT MIX MS LPBK Default: 0000h FUNCTION Mono Output Select (0 = Mix, 1 = MIC) Mic Select (1 = Mic2, 0 = Mic1) ADC/DAC Loopback Mode
Default: na
When the AC-link "Codec Ready" indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the AC-link and AC`97 control and status registers are in a fully operational state. It is the responsibility of the digital controller to further probe the Powerdown Control/Status Register to determine exactly which subsections, if any, are ready. Reserved Registers (Index 28h - 7ah) These are reserved. Do not write to these registers. Vendor ID Registers (Index 7Ch - 7Eh) This register contains the Harris Semiconductor vendor ID. The ID method is a Microsoft's Plug and Play Vendor ID code with F7:0 the first character of that ID, S7:0 the second character and T7:0 the third character. These three characters are ASCII encoded, and they will read back as `HRS'. The REV7:0 field is for the Revision number.
Powerdown Control/Status Register (Index 26h) This register is used to program the HMP9701A's powerdown states and monitor subsystem status. The upper bits of this register are used to power up/down individual sections within the codec as summarized in Table 18.
9
TABLE 20. CONTROL/STATUS REGISTER ADDRESS MAP REG 00h 02h 04h 06h 08h 0Ah 0Ch 0Eh 10h 12h 14h 16h 18h 1Ah 1Ch 1Eh 20h 22h 24h 26h 28h .. 7Ah 7Ch 7Eh Reset Master Volume Reserved Master Volume Mono Reserved PC_BEEP Volume Phone Volume Mic Volume Line In Volume CD Volume Video Volume Aux Volume PCM Out Vol Record Select Record Gain Record Gain Mic General Purpose Reserved Reserved Powerdown Ctrl/Stat Reserved .. Vendor Reserved Vendor ID1 Vendor ID2 NAME D15 X Mute X Mute X Mute Mute Mute Mute Mute Mute Mute Mute X Mute Mute X X X X X .. X F7 T7 D14 0 X X X X X X X X X X X X X X X X X X X X .. X F6 T6 D13 0 ML5 X X X X X X X X X X X X X X X X X PR5 X .. X F5 T5 D12 0 ML4 X X X X X X GL4 GL4 GL4 GL4 GL4 X X X X X X PR4 X .. X F4 T4 D11 0 ML3 X X X X X X GL3 GL3 GL3 GL3 GL3 X GL3 X X X X PR3 X .. X F3 T3 D10 0 ML2 X X X X X X GL2 GL2 GL2 GL2 GL2 SL2 GL2 X X X X PR2 X .. X F2 T2 D9 0 ML1 X X X X X X GL1 GL1 GL1 GL1 GL1 SL1 GL1 X MIX X X PR1 X .. X F1 T1 D8 0 ML0 X X X X X X GL0 GL0 GL0 GL0 GL0 SL0 GL0 X MS X X PR0 X .. X F0 T0 D7 0 X X X X X X X X X X X X X X X LPBK X X X X .. X S7 REV7 D6 0 X X X X X X 20dB X X X X X X X X X X X X X .. X S6 REV6 D5 0 MR5 X MM5 X X GN5 GN5 X X X X X X X X X X X X X .. X S5 REV5 D4 0 MR4 X MM4 X PV3 GN4 GN4 GR4 GR4 GR4 GR4 GR4 X X X X X X X X .. X S4 REV4 D3 0 MR3 X MM3 X PV2 GN3 GN3 GR3 GR3 GR3 GR3 GR3 X GR3 GM3 X X X REF X .. X S3 REV3 D2 0 MR2 X MM2 X PV2 GN2 GN2 GR2 GR2 GR2 GR2 GR2 SR2 GR2 GM2 X X X ANL X .. X S2 REV2 D1 0 MR1 X MM1 X PV0 GN1 GN1 GR1 GR1 GR1 GR1 GR1 SR1 GR1 GM1 X X X DAC X .. X S1 REV1 D0 1 MR0 X MM0 X X GN0 GN0 GR0 GR0 GR0 GR0 GR0 SR0 GR0 GM0 X X X ADC X .. X S0 REV0 DEFAULT na 8000h X 8000h X 8000h 8008h 8008h 8808h 8808h
HMP9701A HMP9701A
8808h 8808h 8808h 0000h 8000h 8000h 0000h X X na X .. X 4852 5300
10
HMP9701A Pinout
HMP9701A (TQFP) TOP VIEW
MONO_OUT RESERVED
AGND
VDD XTL_IN XTL_OUT GND SDATA_OUT BIT_CLK GND SDATA_IN VDD SYNC RESET PC_BEEP
1 2 3 4 5 6 7 8 9 10 11 12
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24
VAA
NC
NC
NC
NC
NC
NC
NC
NC
LINE_OUT_R LINE_OUT_L NC RESERVED NC AFILT3 AFILT2 AFILT1 VREFOUT VREF AGND VAA
VIDEO_R
AUX_R
LINE_IN_L
CD_L
Pin Descriptions
NAME DIGITAL I/O RESET SYNC BIT_CLK SDATA_OUT SDATA_IN ANALOG I/O PC_BEEP 12 I PC Beep. Mono Input for PC Beep pass through to LINE_OUT. This input is attenuated from 0dB to 45dB in 3dB steps and then summed with left and right line outputs (LINE_OUT_L, LINE_OUT_R) Phone. Mono Input from telephony subsystem speaker phone (or DLP - Down Line Phone) Microphone Input 1. The MIC input may be either line-level or -20dB from line-level. In the latter case, a software controlled 20dB gain block may be activated. Microphone Input 2. The MIC input may be either line-level or -20dB from line-level. In the latter case, a software controlled 20dB gain block may be activated. Left Line Input. The left line-level may be selected for recording via one of the stereo ADC's via the Input Mux. In addition, this input can be gained/attenuated from +12dB to -34.5dB in 1.5dB steps and then summed with left line output (LINE_OUT_L). 11 10 6 5 8 I I O I O RESET - This active low signal causes a HMP9701A hardware reset that will return the control/status registers to their default conditions. SYNC - 48kHz sync pulse which defines the beginning of serial audio I/O frames. Note: must be synchronous to BIT_CLK. BIT Clock - 12.288MHz serial data clock derived by dividing down 24.576MHz crystal input. Serial Data Out - Output bit stream that contains audio playback samples as well as control data. This input is sampled on the falling edge of BIT_CLK. Serial Data In - Input bit stream that contains recorded audio samples as well as codec status information. Data output on the rising edge of BIT_CLK. TQFP PIN NUMBER INPUT/ OUTPUT DESCRIPTION
PHONE MIC1 MIC2 LINE_IN_L
13 21 22 23
I I I I
11
LINE_IN_R
CD_R
MIC1
VIDEO_L
CD_GND
PHONE
AUX_L
MIC2
HMP9701A Pin Descriptions
NAME LINE_IN_R TQFP PIN NUMBER 24 (Continued) INPUT/ OUTPUT I DESCRIPTION Right Line Input. The right line-level may be selected for recording via one of the stereo ADC's via the Input Mux. In addition, this input can be gained/attenuated from +12dB to -34.5dB in 1.5dB steps and then summed with right line output (LINE_OUT_R). Left CD Audio Channel. This line-level input may be input to one of the stereo ADC's via the Input Mux. It can also be gained/attenuated from +12dB to -34.5dB in 1.5dB steps and then summed with the Left Line Output (LINE_OUT_L). CD Audio Analog Ground. Right CD Audio Channel. This line-level input is selected for input to one of the stereo ADCs via the Input Mux. It can also be gained/attenuated from +12dB to -34.5dB in 1.5dB steps and then summed with the Right Line Output (LINE_OUT_R). Left Video Input. This line-level input is driven with the left channel audio track from a video source. The signal is selected for input to one of the stereo ADCs via the Input Mux, and it can be gained/attenuated from +12dB to -34.5dB in 1.5dB steps and then summed with Left Line Output (LINE_OUT_L). Right Video Input. This line-level input is driven with the right channel audio track from a video source. The signal is selected for input to one of the stereo ADCs via the Input Mux, and it can be gained/attenuated from +12dB to -34.5dB in 1.5dB steps and then summed with Right Line Output (LINE_OUT_R). Left Auxiliary Input. This line-level input is input to one of the stereo ADCs via the Input Mux. It can also be gained/attenuated from +12dB to -34.5dB in 1.5dB steps and then summed with the Left Line Output (LINE_OUT_L). Right Auxiliary Input. This line-level input is input to one of the stereo ADCs via the Input Mux. It can also be gained/attenuated from +12dB to -34.5dB in 1.5dB steps and then summed with the Right Line Output (LINE_OUT_R). Left Line Output. This line level output is the post-mixed output for the left audio channel. The audio output passes through a Master Volume block that provides attenuation from 0dB to 45dB in 1.5dB steps. Right Line Output. This line level output is the post-mixed output for the right audio channel. The audio output passes through a Master Volume block that provides attenuation from 0dB to 45dB in 1.5dB steps. Mono Output. This user selectable line level output is either the post-mixed output or the microphone input. The mono output passes through a Mono Volume block that provides attenuation from 0dB to 45dB in 1.5dB steps.
CD_L
18
I
CD_GND CD_R
19 20
I I
VIDEO_L
16
I
VIDEO_R
17
I
AUX_L
14
I
AUX_R
15
I
LINE_OUT_L LINE_OUT_R
35 36
O O
MONO_OUT
37
O
MISCELLANEOUS VREF VREFOUT AFILT1 AFILT2 AFILT3 XTL_IN XTL_OUT VAA AGND VDD GND Reserved 27 28 29 30 31 2 3 25, 38 26, 42 1, 9 4, 7 33,39 O O O O O I O I I I I Voltage Reference. Nominal 2.25V reference output. Should not be used to sink or source current. Voltage Reference Out. Nominal 2.25V reference output with 5mA drive capability. Intended a microphone bias. Anti-Alias Filter 1 (Left Record Channel). This pin requires a 1nF capacitor to analog ground for proper operation. Anti-Alias Filter 2 (Right Record Channel). This pin requires a 1nF capacitor to analog ground for proper operation. Anti-Alias Filter 3 (MIC Record Channel). This pin requires a 1nF capacitor to analog ground for proper operation. 24.576MHz Crystal Input. This pin may also be used to input an external 24.576MHz clock source. 24.576MHz Crystal Output. Leave this pin unconnected when using an external clock source. Analog Supply Voltage (5.0V). Analog Ground. Digital Supply Voltage (5.0V). Digital Ground. These pins should NOT be connected externally to any device. They must be left floating!
12
HMP9701A
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V Input Voltages. . . . . . . . . . . . . . . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) TQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only)
Operating Conditions
Temperature Range HMP9701ACN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
Electrical Specifications
PARAMETER
VCC = 5.0V, TA = 25oC, Note 1 HMP9701ACN SYMBOL TEST CONDITION MIN TYP MAX UNITS
POWER SUPPLY CHARACTERISTICS Power Supply Current Digital ICCOP fCLK = 24.576MHz, VDD = 5.0V, Outputs Not Loaded 35 mA
Analog ICCOP fCLK = 24.576MHz, VAA = 5.0V, Outputs Not Loaded Power Supply Rejection (1kHz, 10mVRMS) DIGITAL I/O Input Logic High Voltage Digital Inputs XTL_IN Input Logic Low Voltage Digital Inputs XTL_IN Input Logic Current Output Logic High Voltage Output Logic Low Voltage Three-State Output Current Leakage Rise/Fall Time (SDATA_IN, BIT_CLK) Input/Output Capacitance IIH, IIL VOH VOL IOZ tr, tf CIN Note 1 CLK Frequency = 1MHz, Note 2, All Measurements Referenced to Ground TA = 25oC VDD = Max Input = 0V or 5.25V IOH = -4mA, VDD = Max IOL = 4mA, VDD = Min VIL VDD = Min VIH VDD = Max
-
-
80
mA
-
50
-
dB
2.0 0.7 * VDD -10 2.4 -10 -
-
-
V V
-
0.8 0.3 * VDD +10 0.4 +10 6.0 8
V V A V V A ns pF
Timing Specifications (Notes 1, 5)
HMP9701ACN PARAMETER BIT_CLK Frequency BIT_CLK Period BIT_CLK High BIT_CLK Low tBCP tBCH tBCL SYMBOL TEST CONDITION 24.576MHz Xtal, Note 2 24.576MHz Xtal, Note 2 Note 2 Note 2 MIN 32.56 32.56 TYP 12.288 81.4 MAX 48.84 48.84 UNITS MHz ns ns ns
13
HMP9701A
Timing Specifications (Notes 1, 5) (Continued)
HMP9701ACN PARAMETER Sync Pulse Frequency Sync Period Sync High Sync Low Setup Time SDATA_OUT, SDATA_IN, SYNC to BIT_CLK Hold Time SDATA_OUT, SDATA_IN, SYNC to BIT_CLK RESET Low Pulse Width (for Cold Reset) RESET Inactive to BIT_CLK Start Up (for Cold Reset) SYNC Active High Pulse Width (for Warm Reset) SYNC Inactive Low to BIT_CLK Start Up (for Warm Reset) End of Slot 2 to BIT_CLK, SDATA_IN Low (for AC Link Powerdown) SDATA_OUT to RESET High (for ATE Test Mode) RESET High to Hi-Z (for ATE Test Mode) tSP tSH tSL tSU tHD tCRL tR2BC tSRH tS2BC tPDWN tSU2RST tHZ Note 2 Note 2 SYMBOL TEST CONDITION MIN 15 5 1.0 2*tBCP 2*tBCP 15 TYP 48 20.8 16*tBCP 240*tBCP 1.3 MAX 1 25 UNITS kHz s s s ns ns s ns s ns s ns ns
Digital Filter Characteristics
PARAMETER Passband Transition Band Passband Ripple (0 - 0.4Fs) Stopband Stopband Rejection Group Delay
(Note 2) MIN 0 0.4xFs 0.6xFs 76 TYP MAX 0.4xFs 0.6xFs 0.03 18/Fs UNITS Hz Hz dB Hz dB s
Analog-to-Digital Converters (Notes 1, 3)
PARAMETER Resolution Signal-to-Noise Line Inputs Mic Inputs (Mic Gain = 0dB) Total Harmonic Distortion Line Mic 0.02 0.02 % % 85 85 dB dB MIN TYP 16 MAX UNITS Bits COMMENT Note 2
14
HMP9701A
Analog-to-Digital Converters (Notes 1, 3) (Continued)
PARAMETER Interchannel Isolation Line/Line Line/Mic Line/Aux Line/Video Gain Error (Full Scale) Inter-Channel Gain Mismatch Offset Error Gain Drift (0dB Gain) 80 80 80 80 5 20 100 0.5 200 dB dB dB dB % dB LSB ppm/oC Note 2 Note 2 Note 2 Note 2 Note 2 MIN TYP MAX UNITS COMMENT
Digital-to-Analog Converters
PARAMETER Resolution Signal-to-Noise Total Harmonic Distortion Interchannel Isolation (Line Out) Interchannel Gain Mismatch Gain Error Gain Drift
(Notes 1, 4) MIN 16 80 (Note 1) MIN TYP 22.5 1.5 0.2 46.5 1.5 0.2 46.5 1.5 0.2 46.5 1.5 0.2 45 3 0.2 MAX UNITS dB dB dB dB dB dB dB dB dB dB TYP 17 87 0.02 75 0.35 100 -50 -65 1 MAX 5 UNITS Bits dB % dB dB % ppm/oC dB dB dB Degree Note 2 Note 2 Note 6 Note 2 Note 2 Note 2 COMMENT Note 2
Total Out of Band Energy (28.8kHz - 100kHz) Mute Attenuation (0dB) Audible Out of Band Energy (20kHz - 28.8kHz) Deviation from Linear Phase
Programmable Attenuation/Gain
PARAMETER Record Gain (0dB to 22.5dB) Record Gain Step Size PCM Output Volume Span (+12dB to -34.5dB) PCM Output Volume Span Step Size Master Volume Span for LINE_OUT, MONO_OUT (0dB to -46.5dB) Master Volume Step Size Mixer Input Gain Span for LINE_IN, CD, VIDEO, AUX, PHONE, MIC (+12dB to -34.5dB) Mixer Input Gain Step SIze PC_BEEP Attenuation Span (0dB to 45dB) PC_BEEP Attenuation Step Size
15
HMP9701A
Analog Inputs
(Note 1) PARAMETER Full Scale Input Voltages MIC Inputs with 0dB Gain MIC Inputs with 0dB Gain MIC Inputs with 20dB Gain Enabled MIC Inputs with 20dB Gain Enabled LINE_IN, CD, VIDEO, AUX, and PHONE Inputs LINE_IN, CD, VIDEO, AUX, and PHONE Inputs Input Impedance Input Capacitance 10 (Note 1) PARAMETER Full Scale Output Voltages LINE_OUT and MONO_OUT LINE_OUT and MONO_OUT External Load Impedance External Load Capacitance VREF Output Voltage VREF Drive Current VREF Output Impedance NOTES: 1. TA = 25oC, VAA = VDD = 5.0V 2. Guaranteed but not production tested. 3. Based on 1kHz, Full scale analog tone input; Measurement Bandwidth is 20 to 20kHz, A-weighted. 4. DAC's driven with 1kHz, Full Scale PCM Sine Wave, output measurement bandwidth is 20 to 20kHz, A-weighted. 5. Test performed with CL = 40pF, IOL = 4mA, IOH = -4mA. Input reference level is 1.5V for all inputs. VIH = 3.0V, VIL = 0V. 6. This is measured relative to a nominal output level. 10 2.83 10% 1.0 2.25 10% 5 4 50 VPP VRMS k pF V mA k Note 2 Note 2 MIN TYP MAX UNITS COMMENT 2.83 10% 1.0 0.283 10% 0.1 2.83 10% 1.0 15 VPP VRMS VPP VRMS VPP VRMS k pF Note 2 Note 2 MIN TYP MAX UNITS COMMENT
Analog Outputs
16
HMP9701A ADC/DAC Filter Response Curves
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0.02 0 -0.02 MAGNITUDE (dB) 0.00 0.06 0.13 0.19 0.25 0.31 0.38 0.44 0.50 0.56 0.63 0.69 0.75 0.81 0.88 0.94 1.00 -0.04 -0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -0.18 0.00 0.03 0.06 0.08 0.11 0.14 0.17 0.20 0.23 0.25 0.28 0.31 0.34 0.37 0.40 0.94 0.80 0.42 -0.2
MAGNITUDE (dB)
FREQUENCY (xFS)
FREQUENCY (xFS)
FIGURE 10. ANALOG-TO-DIGITAL FREQUENCY RESPONSE (FULL SCALE LINE INPUTS, 0dB)
FIGURE 11. ANALOG-TO-DIGITAL PASSBAND FREQUENCY RESPONSE (FULL SCALE LINE INPUTS, 0dB)
0.40
0.42
0.45
0.48
0.51
0.54
0.57
0.60
0.63
0.66
0.69
0.72
0.75
0.78
0.00
0.07
0.13
0.19
0.25
0.32
0.38
0.44
0.50
0.57
0.63
0.69
0.75
0.82 0.73
FREQUENCY (xFS)
FREQUENCY (xFS)
FIGURE 12. ANALOG-TO-DIGITAL TRANSITION BAND FREQUENCY RESPONSE (FULL SCALE LINE INPUTS, 0dB)
FIGURE 13. DIGITAL-TO-ANALOG FREQUENCY RESPONSE (FULL SCALE INPUTS, 0dB)
0.05
0 MAGNITUDE (dB) MAGNITUDE (dB)
-0.05
-0.10
-0.15
0.00
0.07
0.14
0.20
0.27
0.34
0.40
0.40
0.46
0.53
0.60
FREQUENCY (xFS)
FREQUENCY (xFS)
FIGURE 14. DIGITAL-TO-ANALOG PASSBAND FREQUENCY RESPONSE (FULL SCALE INPUTS, 0dB)
FIGURE 15. DIGITAL-TO-ANALOG TRANSITION BAND FREQUENCY RESPONSE (FULL SCALE INPUTS, 0dB)
17
0.66
-0.20
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
0.88
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
MAGNITUDE (dB)
MAGNITUDE (dB)
HMP9701A AC Timing Waveforms
RESET tCRL RESET tR2BC SDATA_OUT tSU2RST BIT_CLK, BIT_CLK SDATA_IN tHZ Hi-Z
FIGURE 16. COLD RESET TIMING
FIGURE 17. ATE TEST MODE
tSRH SYNC
tS2BC
BIT_CLK, SDATA_IN
trf 0.8V
trf 2.0V
BIT_CLK
FIGURE 18. WARM RESET TIMING
FIGURE 19. RISE AND FALL TIMES
tPDWN tBCH BIT_CLK tBCL BIT_CLK WRITE TO 26h DATA PR4 = 1 DON'T CARE SLOT 1 SLOT 2
SDATA_IN tSH SYNC tSL
SLOT 12
TAG
SDATA_OUT
SLOT 12
TAG
NOTE: BCLK not to scale. FIGURE 20. CLOCKS FIGURE 21. POWERDOWN
tSU
tHD
BIT_CLK
SDATA_IN SDATA_OUT SYNC
FIGURE 22. DIGITAL SETUP AND HOLD
18
Typical Application Schematic Diagram
AC_LINK INTERFACE SD_OUT 1 BIT_CLK 2 SD_IN 3 TO AC `97 COMPLIANT SYNC 4 CONTROLLER/INTERFACE IC RESET 5 6 1.0F +5V DIGITAL POWER SUPPLY + 1F 0.1F 18pF (NP0) 24.5760MHz (PARALLEL) 0.1F 0.1F 18pF (NP0)
PC_BEEP
1.0F
PHONE
1.0F
AUX LEFT
1.0F
AUX RIGHT
1.0F
HMP9701A
VIDEO RIGHT
1.0F HMP9701A
CD LEFT
RESET SYNC VDD SDATA_IN GND BIT_CLK SDATA_OUT GND XTL_OUT XTL_IN VDD
1.0F
12 PC_BEEP 11 10 9 8 7 6 5 4 3 2 1
VIDEO LEFT
1.0F
MIC2
25 26 27 28 29 30 31 32 33 34 35 36
VAA AGND VREF VREF OUT AFILT1 AFILT2 AFILT3 NC Reserved NC LINE_OUT_L LINE_OUT_R
19
+ 0.1F 0.1F + 1F 1nF (NP0) 1nF (NP0) 1nF (NP0) 0.1F +
+5V ANALOG POWER SUPPLY
1.0F
CD GROUND
1.0F
CD RIGHT
13 14 15 16 17 18 19 20 21 22 23 24 PHONE AUX_L AUX_R VIDEO_L VIDEO_R CD_L CD_GND CD_R MIC1 MIC2 LINE_IN_L LINE_IN_R NC NC NC NC NC NC AGND NC NC Reserved VAA MONO_OUT
48 47 46 45 44 43 42 41 40 39 38 37
1.0F MONO OUT 1F TO 10F 0.1F
1.0F
MIC1
1.0F
1.0F RIGHT LINE OUT 1.0F LEFT LINE OUT REFERNECE VOLTAGE OUT 1F TO 10F
LINE_IN LEFT
1.0F
LINE_IN RIGHT
DIGITAL GND
ANALOG GND
HMP9701A Typical Application Schematic Notes
1. A note about the capacitors used for coupling externally input audio or for outputting audio externally: The capacitance value and the associated circuit impedances will determine the lower frequency cutoff of the audio signal. The designer must determine what the circuit impedances are and select the coupling capacitor value accordingly. Ceramic types (over electrolytic) are highly recommended. 2. The crystal should be a parallel resonant type, frequency is 24.756MHz, initial room temperature tolerance of 50ppm, and a load cap of about 16-20pF. 3. It is recommended to decouple each analog and digital power supply pin with a combination of a small value and large value bypass capacitor. The large value capacitor should be either a tantalum or aluminum electrolytic type. 4. Locate all decoupling capacitors CLOSE to their associated pins on the codec. 5. Please note that all analog inputs and outputs of the HMP9701A codec are at the DC level of VREF and require AC coupling to zero biased signal sources and destinations. 6. Keep all analog input and output traces as short as possible, prevent any coupling from adjacent digital lines. 7. For optimum performance, it is preferred to layout separate analog and digital ground planes, joining them together at a point directly adjacent to the codec (i.e., directly under it). This case is true even if the designer is using a single supply for the codec; the single supply should have adequate decoupling/isolation between the digital and analog sections. 8. When using an external clock source, please feed that signal into the XTL_IN pin and leave the XTL_OUT pin unconnected. Also, do not use any capacitors between XTL_IN and GND or XTL_OUT and GND in that mode.
20

▲Up To Search▲

Price & Availability of HMP9701A

	To Download HMP9701A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .